PCIe lanes, LTSSM training and the PIPE interface
How PCI Express lanes are counted and made up, what happens during LTSSM link training, and where the PIPE interface sits between controller and PHY.
A PCI Express link is built from one or more lanes, and each lane is a pair of unidirectional differential signals, one transmit pair and one receive pair, so a x4 link carries eight physical signal pairs in total. The link width is negotiated at power-up rather than fixed by the slot, and the negotiation is run by a state machine called the LTSSM. Between the link layer logic and the analogue transceiver sits the PIPE interface, a standard parallel bus that lets a controller and a separate PHY chip be designed and tested independently.
How do PCI Express lanes work?
A lane is the smallest unit of a PCI Express link. It consists of two low-voltage differential pairs: one pair driven by the transmitter at each end toward the receiver at the other end, and one pair in the opposite direction. Because the two directions are physically separate, a lane is full duplex, and there is no shared clock wire. The receiver recovers timing from the data stream itself, which is why the specification requires an 8b/10b encoding at 2.5 and 5.0 GT/s and a 128b/130b encoding from 8.0 GT/s onward: the encoding guarantees enough transitions for clock recovery and keeps the running disparity bounded.
Lane count is written as a multiplier. A x1 link has one lane, a x16 link has sixteen. The number after the x is not a speed and not a multiple of bandwidth in a simple linear sense across generations, because the per-lane signalling rate changes with each generation: 2.5 GT/s for Gen1, 5.0 GT/s for Gen2, 8.0 GT/s for Gen3, 16.0 GT/s for Gen4, 32.0 GT/s for Gen5, and 64.0 GT/s for Gen6. Useful bandwidth per lane is lower than the raw rate because of encoding overhead, so a Gen3 lane carries roughly 985 MB/s of payload after the 128b/130b overhead is removed, while a Gen1 lane carries 250 MB/s after 8b/10b.
Widths are not always what the slot suggests. A slot wired for x16 may train to x8 or x4 if some lanes fail, if the connector is physically shorter, or if the device at the other end only implements fewer lanes. The link trains to the highest common width and speed that both ends support, and the result is reported in the Link Status register in configuration space. Readers who want the per-generation numbers and the encoding rules laid out side by side can find them documented in editorial form at PCI Express lanes, which reads the public specifications rather than vendor marketing.
What happens during LTSSM link training?
The LTSSM, or Link Training and Status State Machine, is the sequence of states a port passes through from power-on reset to a fully operational link. It is defined per port, and both ends of a link run their own copy. The states are named and ordered: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Disabled, Loopback, and Hot Reset. Only L0 is the normal operating state; everything before it is preparation, and everything after it is either a power-saving state or a test state.
Detect is where the port checks whether anything is physically attached. The transmitter sends a receiver detection pulse and watches for the change in the electrical characteristics of the line that a terminated receiver produces. If nothing is detected, the port stays in Detect and does not attempt to train.
Polling follows. Both ends exchange training sequences, which are ordered sets of symbols with a defined structure, and they establish bit lock and symbol lock. Bit lock means the receiver's clock recovery circuit is aligned to the incoming bit stream; symbol lock means the receiver knows where symbol boundaries fall. Polling also exchanges the lane polarity, because a lane may be routed with its differential pair inverted on the board, and the receiver can compensate without a layout change.
Configuration is where the link width and lane ordering are settled. Each lane is assigned a lane number, and the two ends agree on which lanes are usable and in what order. Lanes that fail to achieve bit lock are dropped, and the link narrows. This is the state where a x16 slot can end up as a x8 or x4 link. The two ends also agree on the link number and on the speed they will attempt.
Recovery is entered whenever the link needs to change speed, change width, or re-establish synchronisation after an error. It is not a failure state; it is the normal mechanism for a speed change from Gen1 to Gen3 or Gen4, which happens after the link is already up. The port returns to L0 once the change is complete.
L0 is the state in which normal packets flow. From L0 the link can move to L0s, a short electrical idle on each direction independently, or to L1, a deeper low-power state that requires an ordered set handshake. L2 removes power from most of the PHY and is entered before a system sleep. Loopback and Hot Reset are used for testing and for reset propagation respectively.
What is the PIPE interface in PCI Express?
PIPE stands for PHY Interface for the PCI Express architecture. It is a specification, maintained by Intel, that defines the signals between a PCI Express controller, which contains the link and transaction layers, and a separate PHY, which contains the analogue transceiver, the clock recovery, and the serialiser and deserialiser. The point of PIPE is to allow the two halves to be built by different teams or different companies and still connect.
The interface is parallel and synchronous. On the transmit side the controller presents symbols or blocks to the PHY, along with control signals that indicate whether the data is a training sequence, a start of a packet, or an idle. On the receive side the PHY presents recovered symbols and status signals back to the controller, including indications of receiver detection, bit lock, and symbol lock. The width of the data bus scales with the lane count and the generation, so a PIPE implementation for a x16 Gen4 port has a wider and faster bus than one for a x1 Gen1 port.
PIPE is versioned. PIPE 4.0 covers Gen3 rates, PIPE 5.0 covers Gen4, and later revisions cover Gen5 and Gen6, with changes to the width of the interface and to the encoding of status information. A controller and a PHY must agree on the PIPE revision, because the signal set is not backward compatible in every direction. This is one reason a datasheet will state the PIPE revision a device supports rather than only the PCIe generation.
Because PIPE is a published interface, it is also a common point of confusion. The LTSSM lives in the controller, not in the PHY, but many of the conditions the LTSSM reacts to, such as receiver detection and bit lock, are reported across PIPE. A link that fails to train can therefore be a controller problem, a PHY problem, or a board problem, and the PIPE status signals are where the diagnosis starts.
Where the numbers come from
The figures quoted above are not vendor claims. The signalling rates, the encoding schemes, and the LTSSM state names are defined in the PCI Express Base Specification, published by PCI-SIG, which is the standards body that owns the specification and runs the compliance programme. The PIPE specification is published separately by Intel. Both are public documents, and both are revised on dated schedules, which is why a datasheet will cite a revision number and a date rather than a generation alone.
For a reader comparing a board layout to a specification, the practical order is: check the link width and speed reported in configuration space, check the PIPE revision supported by the controller and PHY, and check the LTSSM state the port reaches when the link fails. Those three facts usually separate a layout problem from a configuration problem.
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